Documentation of the UltraZohm
The UltraZohm is a powerful real-time computation platform for research, development, and rapid-control prototyping of power electronics and drive systems. Development is driven by researchers for researches to accelerate research by establishing a common control platform. Having a common platform enables the active research community to focus on publication and results, while the platform development is a shared effort.
High Computational power: Four ARM A53, two ARM R5, and a large FPGA provided by a Xilinx Zynq UltraScale+ MPSoC (ZU9EG).
Hard real-time: Designed to meet modern control systems’ timing requirements for power electronics.
Open Source: Platform with no black-boxes and no barriers for your research. Adapt to your needs and use as you like.
Modularity: Extend the platform with your own hardware (adapter cards), IP-Cores and software components.
Usability: Novice friendly with tutorials and existing codebase. Expert friendly with access to the last bit.
Community: Connect to other researchers working on the same platform and solve infrastructure problems only once!
Documentation: Comprehensive and ever-growing documentation for the Ultrazohm on docs.ultrazohm.com.
Funded: Project development is funded by the BMBF with the research grant KI-Power.
The primary use of the UltraZohm is the research of modern control algorithms for power electronics and drive systems:
Model predictive control of electric drives
Model predictive control of power electronics systems
Renewable energy systems
Multilevel converter including Modular Multilevel Converter (MMC)
Multi-phase motors (m>3)
Special electric motor designs (e.g., transverse flux machine, synchronous reluctance motor)
Machine Learning in drive systems
The project is licensed under the Apache 2.0 license. See LICENSE for details.
- Toolchain installation
- UltraZohm Setup
- System Overview
- Project structure
- How to guides
- Platform Architecture
- RPU Software
- APU Software
- Software Framework
- Software Development Guidelines
- Hardware Abstraction Layer
- Coordinate Transformation
- Field Oriented Control (FOC)
- Linear decoupling
- PMSM config
- Space vector limitation
- Speed Control
- Waveform Generator
- Global configuration
- Unit tests (Ceedling)
- System Time R5
- Matrix math
- Neural network
- Fixed-point library
- Vivado Framework
- IP Cores
- PWM and SS Control V3
- PWM and SS Control V4
- Mux Axi / ISR Trigger Control
- ADC LTC2311
- ADC LTC2311 V3
- Incremental Encoder
- Interlock Module
- AXI Test IP
- Interlock and Deadtime module (2L)
- PT1 plant model
- PMSM Model
- Data Mover / AXI2TCM
- dq-Transformation IP-Core
- Ninephase VSD and Park tranformation IP-Core
- Carrier Board
- Adapter Cards
- Interface to power electronics