IP Cores

IP Cores

• PWM and SS Control V3
  • Idea
  • Basics
  • Designed by
• PWM and SS Control V4
  • IP-Core Hardware
  • Example usage
  • Driver reference
• Mux Axi / ISR Trigger Control
  • PWM counter events
  • Interrupt sources
  • ADC/ISR trigger ratio
  • Example
  • IP-Core
  • Software driver
  • Reference
• ADC LTC2311
  • Idea
  • Basics
  • Designed by
• ADC LTC2311 V3
  • Introduction
  • Software Driver
  • Functional Description
  • I/O Signals (Interface)
  • Terminology
  • Downloads
• Incremental Encoder
  • Configuration
  • Hardware filter of rotational speed
  • IP-Core Hardware
  • Software driver
• Interlock Module
  • Idea
  • Basics
  • Designed by
• AXI Test IP
  • Driver function reference
• Interlock and Deadtime module (2L)
  • Software Driver
  • IP-Core Hardware
  • Vivado Example
• PT1 plant model
  • IP-Core Hardware
  • Example usage
  • Driver reference
• PMSM Model
  • System description
  • IP-Core overview
  • Example usage
  • Driver reference
• Data Mover / AXI2TCM
  • Tightly Coupled Memory (TCM)
  • IP-Core
  • Software driver
  • Reference
• dq-Transformation IP-Core
  • Vitis
  • Vivado
• uz_mlp_three_layer
  • Usage
  • Implementation details
  • Interfaces
  • Sources