PWM and SS Control V3
This IP Core allows to get a Duty Cycle or direct switching states (SS) and outputs the final SS
The idea is, to have one IP Core, which enables during operation, to decide if:
A Duty Cycles are received over the AXI interface
A Duty Cycles are received directly from inside the FPGA
The switching states are received directly from inside the FPGA
Asymmetrical Regular Sampling is used regarding to Grahame Holmes.
The PWM frequency must be between 100 Hz and 100 kHz, otherwise the counter end values must be extended/checked.
An up-down-counter is used.
A flag for 1 cycle is active at the counter maximum and minimum value for triggering subsequent blocks or interrupts.
TriState flags can be used to set both switches of one phase-leg to an off-state.
Sebastian Wendel (THN) in 08/2018