PWM and SS Control V4

The IP core implements a modulation and switching state control unit that generates control signals for power electronic applications for three phase legs of two-level inverter topologies. Interlock and dead-time functionalities are not part of this IP core and are handled in a subsequent IP core. If less than three phase legs are used, unused phase legs can be set to a tristate mode, where neither the top nor the bottom switch of the phase leg are active. For higher phase numbers, multiple instances of this module can be used in the FPGA, each containing its own up-down counter. For synchronizing multiple instances, the counter can be fed to subsequent instances. This feature is the only difference between versions V3 and V4.

The IP core provides two general modes of operation.

  • Pulse width modulator mode (PWM)

  • Direct control of the switching states (SS)

In PWM mode one can choose from two different sources of reference values (duty cycles).

  • Reference values can be sent from the processing system via AXI to the IP core.

  • Reference values can be provided directly from within the FPGA.

The PWM mode uses a 20bit up-down counter and has been tested for switching frequencies of 100 Hz to 100 kHz. For operation especially with lower PWM frequencies one has to adapt the bitsize of the counter.

The IP core uses asymmetrical regular sampling for generation of the pulses:

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Fig. 75 Asymmetric regular sampling according to Grahame Holmes: Pulse Width Modulation For Power Converters

IP-Core Hardware

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Fig. 76 Test bench of PWM and SS Control IP-Core

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Fig. 77 PWM implementation of one phase leg

Example usage

Vivado

  • One instance:

../../../_images/vivado_example.png

Fig. 78 Example implementation in the block design

For further instances, add the IP core to your design as many times as needed and connect them accordingly. For synchronization of instances, feed the count_out port of the first instance into the count_in port of one or several subsequent instances:

../../../_images/vivado_2instances.png

Fig. 79 Example implementation in the block design with two synchronized instances

Warning

  • There will be a delay of about one FPGA clock cycle (measured 16 ns @ 100 MHz) in the counter for a subsequent instance.

  • This means that switching actions are shifted by that delay time between two instances.

A flag for 1 cycle is active at the counter maximum and minimum value for triggering subsequent blocks or interrupts.

Vitis

  • The software driver is called “uz_PWM_SS_2L”

  • Each instance has to be configured by a config struct:

struct uz_PWM_SS_2L_config_t config_1 = {
        .base_address= XPAR_GATES_PWM_AND_SS_CONTROL_V_0_BASEADDR,
        .ip_clk_frequency_Hz=100000000,
        .Tristate_HB1 = false,
        .Tristate_HB2 = false,
        .Tristate_HB3 = false,
        .min_pulse_width = 0.01f,
        .PWM_freq_Hz = 10e3f,
        .PWM_mode = normalized_input_via_AXI,
        .PWM_en = true,
        .use_external_counter = false,
        .init_dutyCyc_A = 0.0f,
        .init_dutyCyc_B = 0.0f,
        .init_dutyCyc_C = 0.0f
};

An instance has to be initialized first and then configured:

PWM_SS_2L_instance_1 = uz_PWM_SS_2L_init(config_1);

After that it can be used in the application. For easy setting of the duty cycles, use the uz_PWM_SS2L_set_duty_cycle function.

Driver reference

typedef struct uz_PWM_SS_2L_t uz_PWM_SS_2L_t

Data type for object UZ_PWM_SS_2L.

enum uz_PWM_SS_2L_PWM_mode

enum for readable configuring of the PWM mode in uz_PWM_SS_2L_hw_SetMode function

Values:

enumerator normalized_input_via_AXI
enumerator normalized_input_via_FPGA
enumerator direct_control_via_FPGA
struct uz_PWM_SS_2L_config_t

Configuration struct for UZ_PWM_SS_2L.

Public Members

uint32_t base_address

Base address of the IP-Core

uint32_t ip_clk_frequency_Hz

Clock frequency of the IP-Core

bool Tristate_HB1

Tristate flag for half-bridge 1, true=on, false=off

bool Tristate_HB2

Tristate flag for half-bridge 2, true=on, false=off

bool Tristate_HB3

Tristate flag for half-bridge 3, true=on, false=off

float min_pulse_width

Minimum pulse width in percent, e.g. 0.01

float PWM_freq_Hz

Switching frequency of PWM mode in Hz

enum uz_PWM_SS_2L_PWM_mode PWM_mode

PWM mode selector

0 = normalized input of reference signal via AXI

e.g. a reference voltage value between 0 and 1

1 = normalized input of reference signal via FPGA

e.g. a reference voltage value between 0 and 1

2 = direct control of switching states via FPGA

bool PWM_en

IP core enable flag

0=disable module, 1=enable module

bool use_external_counter

Flag for choosing the PWM counter source

0 = internal counter source of the instance

1 = counter at port count_in

float init_dutyCyc_A

Initial PWM duty cycle of half-bridge 1, 0…1

float init_dutyCyc_B

Initial PWM duty cycle of half-bridge 2, 0…1

float init_dutyCyc_C

Initial PWM duty cycle of half-bridge 3, 0…1

uz_PWM_SS_2L_t *uz_PWM_SS_2L_init(struct uz_PWM_SS_2L_config_t config)

Initializes an instance of the uz_PWM_SS_2L driver.

Parameters
  • config – Config struct of type uz_PWM_SS_2L_config_t for the IP-Core

Returns

uz_PWM_SS_2L_t* Pointer to initialized instance

void uz_PWM_SS_2L_set_duty_cycle(struct uz_PWM_SS_2L_t *self, float dutyCyc_A, float dutyCyc_B, float dutyCyc_C)

Uses a configuration struct of type uz_PWM_SS_2L_config_t from a uz_PWM_SS_2L_t instance and writes the configuration to the IP-core.

Parameters
  • self – Instance of uz_PWM_SS_2L

  • dutyCyc_A – DutyCycle for Phase A

  • dutyCyc_B – DutyCycle for Phase B

  • dutyCyc_C – DutyCycle for Phase C

void uz_PWM_SS_2L_set_tristate(struct uz_PWM_SS_2L_t *self, bool Tristate_HB1, bool Tristate_HB2, bool Tristate_HB3)

Sets selected half-bridges in a non conducting high-Z tri state mode.

Parameters
  • self – Instance of uz_PWM_SS_2L

  • Tristate_HB1 – Tristate flag for half-bridge 1, true=on, false=off

  • Tristate_HB2 – Tristate flag for half-bridge 2, true=on, false=off

  • Tristate_HB3 – Tristate flag for half-bridge 3, true=on, false=off

void uz_PWM_SS_2L_set_PWM_mode(struct uz_PWM_SS_2L_t *self, enum uz_PWM_SS_2L_PWM_mode PWM_mode)

Sets the input source of gate signals.

Parameters
  • self – Instance of uz_PWM_SS_2L

  • PWM_mode

    There are three modes to chose

    0 = normalized input of reference signal via AXI

    e.g. a reference voltage value between 0 and 1

    1 = normalized input of reference signal via FPGA

    e.g. a reference voltage value between 0 and 1

    2 = direct control of switching states via FPGA