Platform Architecture

The UltraZohm is based on a Xilinx Zynq UltraScale+ MPSoC. The MPSoC features the following processing blocks (GPU omitted):

  • Programmable Logic (PL): FPGA with IP-Cores

  • Application processing unit (APU): four ARM A53 processors

  • Real-time processing unit (RPU): two ARM R5 processors

../../_images/platform_processors_overview.svg

Fig. 37 Processors of the MPSoC and platform architecture of the UltraZohm. Dashed parts of the diagram are on the roadmap but not implemented.

  • Vivado is used to design the PL

  • Vitis is used to program the RPU & APU

RPU

The RPU is in split mode, and only one R5 core is used. The user can either use only one R5 core, use the second R5 core for user applications or activate lock-step operation. One unused core in the framework ensures that users can use lock-step mode for safety-critical applications without changes to the base firmware.

  • See #67 for an example on how to use the second R5 core for user-code

Software design

../../_images/softwareStructure_r5.svg

Fig. 38 Software design of the R5 software. Each software layer ought to depend only on the layer directly below.

IP-Core

IP-Cores are used in Programmable Logic (PL) aka FPGA. They are a reusable component of design logic with a defined interface and behavior that has been verified by its creator. They are comparable to the use of a library for computer programming or a discrete integrated circuit component for printed circuit board design 1 . They can be used for cases, when the compute power of the RPU is not sufficient anymore and an acceleration via hardware is necessary. E.g. deep-learning application are to resource intensive for the processor and can therefore be accelerated on the FPGA with an IP-Core.

  • For further information on the default Vivado project see Default Vivado project.

  • For further information on the existing IP-Cores of the UltraZohm project see IP Cores.

IP-Core driver

IP-Core drivers include higher level functionality to communicate and control the corresponding IP-Core. They are a special and highly relevant case since the flexible usage of IP-cores is a main advantage of the MPSoC. Refer to Software Development Guidelines for an example implementation.

sequenceDiagram framework->>+driver: C=driver_multiply(int A, int B) driver->>+driver_hw: write_portA(uint32_t base_address, int value) driver->>+driver_hw: write_portB(uint32_t base_address, int value) driver_hw->>+IP_Core: uz_axi_write_int32(uint32_t address, int value) driver_hw->>+IP_Core: uz_axi_write_int32(uint32_t address, int value) driver->>+driver_hw: read_portC(uint32_t base_address, int value) driver_hw->>+IP_Core: uz_axi_read_int32(uint32_t address, int value) driver-->>+framework: return (C)

APU

Currently, we use FreeRTOS with the lwIP-Stack to send data from the RPU to a host PC. Only one A53 is used.

Multiple Processors (Roadmap)

There are two ways to use multiple processors on the Zynq Ultrascale:

  • Use Linux on all cores (symmetrical multiprocessing)

  • Use a Hypervisor to partition the processing units (supervised Asymmetric Multi-Processing (AMP))

Note that unsupervised AMP, e.g., using one A53 core with FreeRTOS and one A53 core with Baremetal or using multiple A53 cores with FreeRTOS/Baremetal without a Hypervisor, is not supported for the UltraScale 1 (p. 19). XEN Hypervisor is recommended by Xilinx 1 (p. 67).

Sources

1(1,2,3)

Software Guide UG1228

2

Semiconductor intellectual property core <https://en.wikipedia.org/wiki/Semiconductor_intellectual_property_core>