Default Vivado project

The default Vivado project uses vendor IP-Cores as well as IP-Cores from the Ultrazohm repository (IP Cores) to provide a starting point for users. It is located in ultrazohm_sw/vivado/project/ultrazohm.xpr and can be generated using the build.tcl script (see Vivado build tcl scripts). Fig. 101 shows the default project. It is split into the following different parts:

  1. Inputs ports from the digital and analog adapter cards

  2. The processing system (PS) with R5 and A53.

  3. uz_system with clocks, interrupts, AXI infrastructure, and IP-Cores for system functions.

  4. The IP-Cores to interface the adapter cards on A1, A2, and A3.

  5. The ouput ports to digital and analog adapter cards.

  6. The uz_user subsystem where user specific IP-Cores should be placed.

  7. The IP-Cores to interface the digital adapter cards on D1, D2, D3, D4, and D5.


Fig. 101 Default Vivado project of the UltraZohm. Add custom IP-Cores to uz_user sub-block.

The sub-blocks (Create hierarchy in Vivado) provide the following functionality:

  • smartconnect_0 to connect AXI signals to the PS

  • uz_enable handles enabling the output signals as well as the data mover

  • uz_clocks generates 100 MHz, 50 MHz, 10 MHz clocks for IP-Cores and matching reset signals

  • timer_update_64bit is the counter used for System Time R5

  • Data Mover / AXI2TCM transfers data from PL to PS

  • Interrupt controls the interrupts of the R5 in the PL (Interrupts R5)