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UltraZohm documentation

  • Getting started
  • Guide
  • Hardware
  • Software
  • IP-Cores
  • Getting started
  • Guide
  • Hardware
  • Software
  • IP-Cores

Section Navigation

  • PWM and SS Control V4
  • Mux Axi / ISR Trigger Control
  • ADC LTC2311 V3
  • Incremental Encoder
  • AXI Test IP
  • Interlock and Deadtime module (2L)
  • PT1 plant model
  • PMSM Model
  • Inverter Model
  • Data Mover / AXI2TCM
  • dq-Transformation IP-Core
  • uz_mlp_three_layer
  • uz_dac_spi_interface
  • RS Flip Flop
  • Inverter Adapter
  • CIL PMSM
    • Multi-phase PMSM Model
    • Multi-phase VSD and Park transformation IP-Core
    • Inverter Model
    • Six-phase CIL Example
  • Temperature Card IP-Core V1
  • Resolver Interface
  • Resolver PL Interface
  • AXI GPIO
  • IP-Cores

IP-Cores#

  • PWM and SS Control V4
  • Mux Axi / ISR Trigger Control
  • ADC LTC2311 V3
  • Incremental Encoder
  • AXI Test IP
  • Interlock and Deadtime module (2L)
  • PT1 plant model
  • PMSM Model
  • Inverter Model
  • Data Mover / AXI2TCM
  • dq-Transformation IP-Core
  • uz_mlp_three_layer
  • uz_dac_spi_interface
  • RS Flip Flop
  • Inverter Adapter
  • CIL PMSM
  • Temperature Card IP-Core V1
  • Resolver Interface
  • Resolver PL Interface
  • AXI GPIO

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ML-MT-Optimized control during OPF

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PWM and SS Control V4

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