CPLD

The Carrier Board has one CPLD for each digital interface slot (D1-D5). They are used to shift the voltage level from 1.8V (FPGA) to 3.3V (Adapter Cards) . Additional safety can be implemented, e.g. checking switch combinations or ensuring deadtime.

• Install Lattice Toolchain (CPLD)
  • Diamond Programmer
  • ispLEVER Classic
• Create a CPLD program using ABEL
  • Step-by-step
• Programming the CPLD
  • CPLD Versions
  • Step-by-step for Trenz TE0790
  • Step-by-step for uz_per_jtag
  • Known issues
    • Not possible to find the CPLDs
  • See also