Create a CPLD program using Lattice Diamond#

The main goal of this section is to describe the necessary steps for creating a simple program for the MACHXO2 CPLDs on the UltraZohm \(\geq\) Rev05. All signals from the FPGA to the digital adapter cards have to pass through the CPLDs.

D-Slot CPLDs#

Everything is programmed inside the project uz_d_slots.ldf. It is located in the repository at MACHXO2/D_Slot_CPLD_LCMXO2-2000HC-4TG100C/uz_d_slots/. Here we can create additional implementations for the CPLD. The advantage of having all CPLD programs within one project is that VHDL code from other files can be used, but every file has its own constraints (e.g. all signals function as inputs versus all signals function as outputs).

Step-by-step#

  1. Open Lattice Diamond and there the project uz_d_slots.ldf. Click Open.

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  1. For creating a new CPLD program click Clone Implementation by right click on the template template_dslots and the subsequent contex menu.

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  1. Provide a proper Name and give the Directory the same name. Select the Default Strategy to Strategy1 and check the box Copy files into new implementation source directory. Click OK.

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  1. In order to modify your new implementation, right click on it an Set as Active Implementation.

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  1. The template VHDL File is copied to the source directory. Remove it by right clicking the InputFile and Remove .

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  1. Right click the project file and Open Containing Folder.

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  1. Edit the template VHDL File and name it according to your project.

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  1. Add the renamed VHDL File to your project by right clicking the InputFiles - Add- Existing File .

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  1. Checkout Files of type: - All Files, navigate to your source directory and add your previously renamed VHDL File.

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  1. Write VHDL Code for the CPLD and save it.

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  1. When saving Diamond automatically checks the code and gives feed back. If everything is fine it looks as below.

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  1. Switch to the Process view.

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  1. Start the processes shown below by double-clicking on them, one after another.

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  1. If every process passed it looks as shown below. You can now use the exported JEDEC File to flash a CPLD with the Diamond Programmer Programming the CPLD.

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15. Constraints for the D-Slot CPLDs are provided in the existing uz_d_slots.ldf project. If ever needed, one can check and modify the constraints by opening the Spreadsheet View.

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S3C#

The same procedure can be applied to create a program for the S3C. Everything is programmed inside the project UZ_Rev05_S3C.ldf. It is located in the repository at MACHXO2/S3C_CPLD_LCMXO2-4000HC-4TG144C/.

Danger

Modifying the bitstream of the S3C fundamentally alters the startup and power-down behavior of the UZ. Such changes may render the carrier board inoperative, requiring physical recovery through soldering. Exercise caution in your actions within this context.

Note

Check the schematic from the Carrierboard to see, which signals are inputs/outputs or bidirectional. The Pins have a dedicated direction and cannot be freely configured.

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