Create new Project#

Note

In the UltraZohm software, vitis_generate_UltraZohm_workspace.tcl takes care of this, see Tcl Scripts for more information.

Here you can find a nice tutorial on how to get started with Vitis.

Workspace configuration#

  1. Export the hardware file

../../../_images/vitis_create1.png

  1. Define the Vitis workspace

../../../_images/vitis_create2.png

  1. Afterwards a file “zusys_wrapper.xsa” will be created which describes the hardware description on the FPGA and includes the Bitstream (in older versions/before vitis/with SDK, this was called “zusys_wrapper.hdf”)

../../../_images/vitis_create3.png

  1. Afterwards we can start Vitis, which was in former days the SDK

../../../_images/vitis_create4.png

The Platform Project#

  1. Create a “Platform Project”

../../../_images/vitis_create5.png ../../../_images/vitis_create6.png ../../../_images/vitis_create7.png ../../../_images/vitis_create8.png

  1. Activate the creation of a Boot Image

../../../_images/vitis_create9.png

  1. Afterwards, you have the Platform project ready. You have to do this only once.

../../../_images/vitis_create10.png

  1. Add the LW-IP-Ethernet IP-Core

    1. Right click on the FreeRTOS BSP

    2. Modify BSP settings

    ../../../_images/vitis_create11.png

    1. Add the IP-Core

    ../../../_images/vitis_create12.png

  2. Build the platform especially if the platform is “out-of-date”

../../../_images/vitis_create13.png

The Application Project#

Next step will be to create an “Application Project” for each different solution.

FreeRTOS#

  1. In our case we have one processor of the A53 for the FreeRTOS:

../../../_images/vitis_create14.png ../../../_images/vitis_create15.png ../../../_images/vitis_create16.png

  1. If the necessary Platform is not shown, press the “+” and select the “ProjectName.xpfm” file from the path manually.

../../../_images/vitis_create17.png

  1. The following step works only if the LW-IP was included before:

../../../_images/vitis_create18.png

  1. Press Finish

../../../_images/vitis_create19.png

  1. You will see the name of the “Platform Project”, on which the “Application Project” is based on, in the yellow brackets behind the application.

Bare Metal#

We will use one processor of the R5 for the Bare Metal application

  1. Since during creation of the “platform Design” we just created a “System project” for the A53_0, we now have to do the same manually for the R5

  2. Right click on the “Vitis_UltraZohm” and add a domain

../../../_images/vitis_create20.png ../../../_images/vitis_create21.png

  1. You should see the domain now. Rename the FreeRTOS to just freertos

../../../_images/vitis_create22.png

  1. Rebuild the platform project since it is out-of-date (yellow comment)

  2. Add the new application project.

../../../_images/vitis_create23.png

Side comment: If there is already another Platform and Application present in VITIS, it may happen, that the new domain is not visible. In this case, it is necessary to delete the old/other Platform and Application. Afterwards, the new domain, e.g. for BareMetal is visible.

../../../_images/vitis_create24.png ../../../_images/vitis_create25.png

C-Project Setup#

The project structure should be ready at this time.

  1. Include the source (.c) and header (.h) files

../../../_images/vitis_create26.png

  1. Make sure that the UltraZohm linker script is included.

../../../_images/vitis_create27.png

  1. At this moment the system is ready for modifications

../../../_images/vitis_create28.png

  1. You can start a debug session now

../../../_images/vitis_create29.png