Overview of the ARM Pins

In the following table you will find an overview of the pin mapping of the SoC MIO pins (fixed pins of the SoC’s Processing System). All connector-accessible MIO pins – i.e., those having an X… assignment in column CB-Pin – are labeled with the associated net label/name (of the carrier board) in the fifth column and the connector pin in the CB-Pin column (CB –> Carrier Board). The connectivity between MIO pins and the frontpanel I/Os – four user LEDs and three buttons – is shown by column FP_.

Itemized list of MIO-related changes next to Overview of the MIO Pins (Rev04):

• The retrofitted Ethernet PHY resets on Rev04 (cf. Ethernet PHY Reset pins (≤ Rev04)) are moved from MIO26/27 to the S3C

  • MIO26 becomes a PMU spare (with IRQ capability)

  • MIO27 becomes part of DPaux

• Three LEDs (PS_1V8_GPIO2/3/4) on MIO33/34/39 and two frontpanel switches (PS_1V8_GPIO5/7) on MIO40/30 are moved to MIO56-60

  • MIO30 becomes DPaux (with MIO27-29)

  • MIO33 becomes a PMU spare

  • MIO34 becomes CS1 of SPI1

  • MIO39 becomes CS2 of SPI0

  • MIO40 becomes CS1 of SPI0

• The “External STOP” (isoEmergencyStop) on MIO31 is moved to MIO61, making room for a PMU spare (without IRQ capability)

• PS_ANL_sharedA on MIO45 is moved to MIO62, making room for CD of the µSD

• MIO52 is reserved for the PCIe reset

• The remaining isoGPIOs (MIO53-55) are assigned to power messaging (i.e., a ready-to-poweroff output and – optionally, as the APU shall use I²C for it – a power button input), an SMBus-like IRQ line for the user I²C and a reset for its bus mux/switch

Note that all changes affect only MIO pins that are used as GPIO in Rev04, which

• makes the Vivado design of Rev04 compatible to Rev05 (as GPIO remapping is already supported in software, cf. the uz_MioGpio module or the Platform Framework), and

• limits (eventually required) changes to the Vivado design solely(!) to making any of the aforementioned new hardware features available, at a later point in time.

Table 67 Overview of the MIO Pins (Rev05)

SoC-Pin	Interface Type	Xilinx Name	SoM-Pin	Schematic, PCB, Connector Label	CB-Pin	FP_
MIO0	QSPI	sclk_out
MIO1	QSPI	miso_mo1
MIO2	QSPI	mo2
MIO3	QSPI	mo3
MIO4	QSPI	mosi_mi0
MIO5	QSPI	n_ss_out
MIO6	QSPI	clk_for_lpbk	NC!
MIO7	QSPI	n_ss_out_upper
MIO8	QSPI	mo_upper[0]
MIO9	QSPI	mo_upper[1]
MIO10	QSPI	mo_upper[2]
MIO11	QSPI	mo_upper[3]
MIO12	QSPI	sclk_out_upper
MIO13	GPIO0	gpio0[13]	J3-72	tbd → tbd	Xtbd-tbd	LED1
MIO14	I2C_0	scl(_out)	J3-74	PLL_SCL → PS_I2C_SCL_3V3	SoM; A1-3; D1-5; CPLDs
MIO15	I2C_0	sda(_out)	J3-76	PLL_SDA → PS_I2C_SDA_3V3	Cf. MIO14
MIO16	I2C_1	scl(_out)	J3-78	PS_I2C1_SCL → EXT_I2C1_SCL	X10-6
MIO17	I2C_1	sda(_out)	J3-80	PS_I2C1_SDA → EXT_I2C1_SDA	X10-12
MIO18	UART0	rxd	J3-82	PS_UART0_RX	X8-7
MIO19	UART0	txd	J3-71	PS_UART0_TX	X8-3
MIO20	UART1	txd	J3-73	PS_UART1_TX → EXT_UART1_TX	X10-11
MIO21	UART1	rxd	J3-75	PS_UART1_RX → EXT_UART1_RX	X10-5
MIO22	CAN_0	phy_rx	J3-77	CAN0_RXD	?P1A-1?
MIO23	CAN_0	phy_tx	J3-79	CAN0_TXD	?P1A-2?
MIO24	CAN_1	phy_tx	J3-81	CAN1_TXD	?P1B-2?
MIO25	CAN_1	phy_rx	J3-83	CAN1_RXD	?P1B-1?
MIO26²	PMU	gpi[0]	J3-88	tbd → tbd	TPtbd	IRQ
MIO27²	DP	aux_data_out	J3-90	tbd → tbd	Xtbd-tbd	Via
MIO28²	DP	hot_plug_detect	J3-92	tbd	Xtbd-tbd	S3C
MIO29²	DP	aux_data_oe	J3-94	tbd	Xtbd-tbd	to
MIO30²	DP	aux_data_in	J3-96	tbd	Xtbd-tbd	FP.
MIO31²	PMU	gpi[5]	J3-98	tbd	TPtbd	!IRQ
MIO32¹	SPI_1	sclk(_out)	J3-87	tbd → tbd	Xtbd-tbd	iso-
MIO33¹	PMU	gpo[1]	J3-89	tbd → tbd	Xtbd-tbd	Alt.: CS2
MIO34¹	SPI_1	n_ss_out[1]	J3-91	tbd → tbd	Xtbd-tbd	Alt.: PMU
MIO35¹	SPI_1	n_ss_out[0]	J3-93	tbd → tbd	Xtbd-tbd	SPI
MIO36¹	SPI_1	miso	J3-95	tbd → tbd	Xtbd-tbd	to
MIO37¹	SPI_1	mosi	J3-97	tbd → tbd	Xtbd-tbd	FP.
MIO38	SPI_0	sclk(_out)	J3-102	tbd → tbd		2x to
MIO39	SPI_0	n_ss_out[2]	J3-104	tbd → tbd		S3C-
MIO40	SPI_0	n_ss_out[1]	J3-106	tbd → tbd		& 5x
MIO41	SPI_0	n_ss_out[0]	J3-108	tbd → tbd		to D-
MIO42	SPI_0	miso	J3-110	tbd → tbd		CP-
MIO43	SPI_0	mosi	J3-112	tbd → tbd		LDs.
MIO44	GPIO1	gpio1[44]	J3-101	tbd → tbd	Xtbd-tbd	SW1 (sys)
MIO45	SD-Card1	cd_n	J3-103	(via S3C to µSD)
MIO46	SD-Card1	data_io[0]	J3-105
MIO47	SD-Card1	data_io[1]	J3-107
MIO48	SD-Card1	data_io[2]	J3-109
MIO49	SD-Card1	data_io[3]	J3-111
MIO50	SD-Card1	cmd_io	J3-113
MIO51	SD-Card1	clk_out	J3-114
MIO52	PCIe	reset_n	J3-118			to FP
MIO53	GPIO2	gpio2[53]	J3-120			Pwr
MIO54	GPIO2	gpio2[54]	J3-122			I²C0i
MIO55	GPIO2	gpio2[55]	J3-124			& rst
MIO56	GPIO2	gpio2[56]	J3-126			LED2
MIO57	GPIO2	gpio2[57]	J3-128			LED3
MIO58	GPIO2	gpio2[58]	J3-117			LED4
MIO59	GPIO2	gpio2[59]	J3-119			SWx
MIO60	GPIO2	gpio2[60]	J3-121			SWy
MIO61	GPIO2	gpio2[61]	J3-123			eSTP
MIO62	GPIO2	gpio2[62]	J3-125	PS_ANL_sharedA	X5*-56
MIO63	GPIO2	gpio2[63]	J3-127			spare
MIO64	Ethernet	rgmii_tx_clk	J3-131
MIO65	Ethernet	rgmii_txd[0]	J3-133
MIO66	Ethernet	rgmii_txd[1]	J3-135
MIO67	Ethernet	rgmii_txd[2]	J3-137
MIO68	Ethernet	rgmii_txd[3]	J3-139
MIO69	Ethernet	rgmii_tx_ctl	J3-141
MIO70	Ethernet	rgmii_rx_clk	J3-132
MIO71	Ethernet	rgmii_rxd[0]	J3-134
MIO72	Ethernet	rgmii_rxd[1]	J3-136
MIO73	Ethernet	rgmii_rxd[2]	J3-138
MIO74	Ethernet	rgmii_rxd[3]	J3-140
MIO75	Ethernet	rgmii_rx_ctl	J3-142
MIO76	MDIO3	gem3_mdc	J3-143
MIO77	MDIO3	gem3_mdio(…)	J3-144

Keys:

• ¹) PMU-Out

• ²) PMU-In

Pin capabilities

For detailed information, see the Xilinx Technical Reference Manual of the Zynq UltraScale+ aka UG1085 (i.e., chapter Multiplexed I/O and table MIO Interfaces).