Changeset#

Associated Repositories w/ toplevel issues#

Overview of Change Issues vs. Repositories#

Table 65 Changeset Rev05-UZC#

Bugfix/

Issue #

Further

Tagline

carrier

issue #s

Fix/Extend supply sequencing (towards dig. 5V cards)

117

36 (dVlt)

Optimize DC/DC converters of CAN & SPI (w.r.t. costs)

121

Implement resets of Ethernet PHYs

122

Improve onboard I²Cs (add mux, unify with MZ, …)

123, 126

Add support for adapter card identification [including detection of signal directions on dig. volt. (dVlt) cards]

138 and uz_sw PR444

6 (D slot templ.), [37 dVlt]

Integrate SSD, EEPROMs, frontpanel GPIO, PCIe, etc.

124

5 (lilac board)

Integrated isolated dual-JTAG solution

Replace (D slot) CPLDs

127

Redesign front (and back?) panel

130, 141

FP8 / 9 / 10, H16

Add system fan (connectors)

H17

Redesign isoGPIOs and make them available on panel

134

Remap PS_ANL_shared to/and fix CD of the µSD card

128, 135

(Migrate SoM from TE0808 to TE0818

131)

Add System&Safety CPLD

143, 132

Move PSU to far-right corner of chassis

136

branch H repo

Protect the VIn, 5V and 3V3 rails at the slots (cf. spec)

146

Make PL MGT transceivers usable

133