Overview of the ARM Pins

In the following table you will find an overview of the pin mapping of the SoC MIO pins (ARM pins of the SoCs’ Processing System). All accessible MIO pins through a connector are labeled with the appropriate carrier board schematic label in column Schematic Connector Label and the connector pin in column CB-Pin (CB –> Carrier Board). The connectivity between MIO pin and the four user LEDs is shown by column LED.

Table 79 Overview of the MIO Pins
SoC-Pin	Interface Type	Xilinx Name	SoM-Pin	Schematic Connector Label	CB-Pin	LED
MIO0	QSPI	sclk_out
MIO1	QSPI	io[1]
MIO2	QSPI	io[2]
MIO3	QSPI	io[3]
MIO4	QSPI	si_mio[0]
MIO5	QSPI	n_ss_out
MIO6	QSPI	clk_for_lpbk
MIO7	QSPI	n_ss_out_upper
MIO8	QSPI	upper_io[0]
MIO9	QSPI	upper_io[1]
MIO10	QSPI	upper_io[2]
MIO11	QSPI	upper_io[3]
MIO12	QSPI	sclk_out_upper
MIO13	GPIO	io[13]	J3-72	EXT_GPIO1	X13-3	LED1
MIO14	I2C_0	scl	J3-74
MIO15	I2C_0	sda	J3-76
MIO16	I2C_1	scl	J3-78	EXT_I2C1_SCL	X10-6
MIO17	I2C_1	sda	J3-80	EXT_I2C_SDA	X10-12
MIO18	UART0	rxd	J3-82	PS_UART0_RX	X8-7
MIO19	UART0	txd	J3-71	PS_UART0_TX	X8-3
MIO20	UART1	txd	J3-73	EXT_UART1_TX	X10-11
MIO21	UART1	rxd	J3-75	EXT_UART1_RX	X10-5
MIO22	CAN_0	phy_rx	J3-77	CAN_RXD1	P1A-1
MIO23	CAN_0	phy_tx	J3-79	CAN_TXD1	P1A-2
MIO24	CAN_1	phy_tx	J3-81	CAN_TXD2	P1B-2
MIO25	CAN_1	phy_rx	J3-83	CAN_RXD2	P1B-1
MIO26	PS_JTAG	tck	J3-88	PJTAG0_TCK	X9-9
MIO27	PS_JTAG	tdi	J3-90	PJTAG0_TDI	X9-5
MIO28	PS_JTAG	tdo	J3-92	PJTAG0_TDO	X9-13
MIO29	PS_JTAG	tms	J3-94	PJTAG0_TMS	X9-7
MIO30	GPIO1	io[4]	J3-96	PS_DIG_GPIO_01	X6-77
MIO31	GPIO1	io[5]	J3-98	PS_DIG_GPIO_02	X6-78
MIO32	SPI_1	sclk	J3-87	isoSPI_SCLK_3V3	X12-5
MIO33	GPIO1	io[7]	J3-89	EXT_GPIO2	X13-4	LED2
MIO34	GPIO1	io[8]	J3-91	EXT_GPIO3	X13-11	LED3
MIO35	SPI_1	n_ss_out[0]	J3-93	isoSPI_CS_3V3	X12-6
MIO36	SPI_1	miso	J3-95	isoSPI_MISO_3V3	X12-3
MIO37	SPI_1	mosi	J3-97	isoSPI_MOSI_3V3	X12-2
MIO38	SPI_0	sclk	J3-102	EXT_SPI0_SCLK	X10-4
MIO39	GPIO1	io[13]	J3-104	EXT_GPIO4	X13-12	LED4
MIO40	GPIO1	io[14]	J3-106	EXT_GPIO5	X13-6
MIO41	SPI_0	n_ss_out[0]	J3-108	EXT_SPI0_CS	X10-10
MIO42	SPI_0	miso	J3-110	EXT_SPI0_MISO	X10-9
MIO43	SPI_0	mosi	J3-112	EXT_SPI0_MOSI	X10-3
MIO44	GPIO1	io[18]	J3-101	PS_ANL_GPIO_01	X5-56
MIO45	GPIO1	io[19]	J3-103	PS_ANL_GPIO_02	X5-59
MIO46	SD-Card1	data_io[0]	J3-105
MIO47	SD-Card1	data_io[1]	J3-107
MIO48	SD-Card1	data_io[2]	J3-109
MIO49	SD-Card1	data_io[3]	J3-111
MIO50	SD-Card1	cmd_io	J3-113
MIO51	SD-Card1	clk_out	J3-114
MIO52	GPIO2	io[0]	J3-118	PS_GPIO7	X13-14
MIO53	GPIO2	io[1]	J3-120	PS_GPIO6	X13-7
MIO54	GPIO2	io[2]	J3-122
MIO55	GPIO2	io[3]	J3-124	PS_GPIO8	X13-15
MIO56	GPIO2	io[4]	J3-126
MIO57	GPIO2	io[5]	J3-128
MIO58	GPIO2	io[6]	J3-117
MIO59	GPIO2	io[7]	J3-119
MIO60	GPIO2	io[8]	J3-121
MIO61	GPIO2	io[9]	J3-123
MIO62	GPIO2	io[10]	J3-125
MIO63	GPIO2	io[11]	J3-127
MIO64	Ethernet	rgmii_tx_clk	J3-131
MIO65	Ethernet	rgmii_txd[0]	J3-133
MIO66	Ethernet	rgmii_txd[1]	J3-135
MIO67	Ethernet	rgmii_txd[2]	J3-137
MIO68	Ethernet	rgmii_txd[3]	J3-139
MIO69	Ethernet	rgmii_tx_ctl	J3-141
MIO70	Ethernet	rgmii_rx_clk	J3-132
MIO71	Ethernet	rgmii_rxd[0]	J3-134
MIO72	Ethernet	rgmii_rxd[1]	J3-136
MIO73	Ethernet	rgmii_rxd[2]	J3-138
MIO74	Ethernet	rgmii_rxd[3]	J3-140
MIO75	Ethernet	rgmii_rx_ctl	J3-142
MIO76	MDIO3	gem3_mdc	J3-143
MIO77	MDIO3	gem3_mdio	J3-144

Interface description

The following diagrams show the signal flow of all communication interfaces.

I2C0

I2C0 is shared over all Digital- and Analog-Adapter-Sockets –> this is in order to read out errors after the “Collective Fault” switched of in an error case!

I2C0 is also used to configure the PLL chip Si5345 during start-up, which sets up all clocks. See the Trenz-Elektronik Wiki

graph TD SoM[SoM] SoM --> |1.8 V| U4A(CPLD U4A) SoM --> |1.8 V| U4B(CPLD U4B) SoM --> |1.8 V| U4C(CPLD U4C) SoM --> |1.8 V| U4D(CPLD U4D) SoM --> |1.8 V| U4E(CPLD U4E) SoM --> |1.8 V| U30[Level Shifter U30] U30 --> |3.3 V| A1(A1) U30 --> |3.3 V| A2(A2) U30 --> |3.3 V| A3(A3) U30 --> |3.3 V| D1(D1) U30 --> |3.3 V| D2(D2) U30 --> |3.3 V| D3(D3) U30 --> |3.3 V| D4(D4) U30 --> |3.3 V| D5(D5)

I2C1

I2C1 is for free use but without isolated interface

graph LR SoM[SoM] SoM --> |1.8 V| U14[Level Shifter U14] U14 --> |3.3 V| X10

UART0

UART0 is available at the XMOD connector for the TE0790 module (JTAG interface)

graph LR SoM[SoM] SoM --> |1.8 V| X8

UART1

UART_1 is for free use, but without isolated interface

graph LR SoM[SoM] SoM --> |1.8 V| U14(Level Shifter, U14) U14 --> |3.3 V| X10

CAN0

graph LR SoM[SoM] SoM --> |1.8 V| U6A(CAN PHY, U6A Isolation) SoM --> |1.8 V| P1A(P1A) U6A --> |5.0 V| X7A

CAN1

graph LR SoM[SoM] SoM --> |1.8 V| U6B(CAN PHY, U6B Isolation) SoM --> |1.8 V| P1B(P1B) U6B --> |5.0 V| X7B

SPI0

graph LR SoM[SoM] SoM --> |1.8 V| U14(Level Shifter, U14) U14 --> |3.3 V| X10

SPI1

graph LR SoM[SoM] SoM --> |1.8 V| U17(Level Shifter, U17) U17 --> |3.3 V| U18(Digital Isolator, U6A Isolation) U18 --> |3.3 V| X12

Ethernet

graph LR SoM[SoM] SoM --> |1.8 V| U2(U2 ETH PHY) U2 --> |3.3 V| X4(X4 RJ45)

GPIO0, GPIO1, GPIO2

graph LR SoM[SoM] SoM --> |1.8 V| U25(U25 Level Shifter) U25 --> |3.3 V| U24(U24 Digital Isolator) U25 --> |3.3 V| U26(U26 Digital Isolator) U24 --> |3.3 V| IO_protection(I/O Protection TVS, PTC Fuse) U26 --> |3.3 V| IO_protection IO_protection --> X13 SoM --> |1.8 V| LEDs SoM --> |1.8 V| X11

PJTAG

graph LR SoM[SoM] SoM --> |1.8 V| X9

Pin capabilities

For detailed information see the Xilinx Technical Refrence Manual UG1085 (v2.2) for the Zynq UltraScale+

The MIO interface description can be found on page under chapter 28 Multiplexed I/O (Table 28-3: MIO Interfaces).