Overview of the ARM Pins#

In the following table you will find an overview of the pin mapping of the SoC MIO pins (fixed pins of the SoC’s Processing System). All connector-accessible MIO pins – i.e., those having an X… assignment in column CB-Pin – are labeled with the associated net label/name (of the carrier board) in the fifth column and the connector pin in the CB-Pin column (CB –> Carrier Board). The connectivity between MIO pins and the frontpanel I/Os – four user LEDs and three buttons – is shown by column FP_.

Table 64 Overview of the MIO Pins (Rev04)#

SoC-Pin

Interface Type

Xilinx Name

SoM-Pin

Schematic, PCB, Connector Label

CB-Pin

FP_

MIO0

QSPI

sclk_out

MIO1

QSPI

miso_mo1

MIO2

QSPI

mo2

MIO3

QSPI

mo3

MIO4

QSPI

mosi_mi0

MIO5

QSPI

n_ss_out

MIO6

QSPI

clk_for_lpbk

NC!

MIO7

QSPI

n_ss_out_upper

MIO8

QSPI

mo_upper[0]

MIO9

QSPI

mo_upper[1]

MIO10

QSPI

mo_upper[2]

MIO11

QSPI

mo_upper[3]

MIO12

QSPI

sclk_out_upper

MIO13

GPIO0

gpio0[13]

J3-72

PS_1V8_GPIO1 → FrontPanel_LED1

X18-14

LED1

MIO14

I2C_0

scl(_out)

J3-74

PLL_SCL → PS_I2C_SCL_3V3

SoM; A1-3; D1-5; CPLDs

MIO15

I2C_0

sda(_out)

J3-76

PLL_SDA → PS_I2C_SDA_3V3

Cf. MIO14

MIO16

I2C_1

scl(_out)

J3-78

PS_I2C1_SCL → EXT_I2C1_SCL

X10-6

MIO17

I2C_1

sda(_out)

J3-80

PS_I2C1_SDA → EXT_I2C1_SDA

X10-12

MIO18

UART0

rxd

J3-82

PS_UART0_RX

X8-7

MIO19

UART0

txd

J3-71

PS_UART0_TX

X8-3

MIO20

UART1

txd

J3-73

PS_UART1_TX → EXT_UART1_TX

X10-11

MIO21

UART1

rxd

J3-75

PS_UART1_RX → EXT_UART1_RX

X10-5

MIO22

CAN_0

phy_rx

J3-77

CAN0_RXD

?P1A-1?

MIO23

CAN_0

phy_tx

J3-79

CAN0_TXD

?P1A-2?

MIO24

CAN_1

phy_tx

J3-81

CAN1_TXD

?P1B-2?

MIO25

CAN_1

phy_rx

J3-83

CAN1_RXD

?P1B-1?

MIO26

PS_JTAG

tck

J3-88

PJTAG0_TCK → Reset PHY0 (U2)

X9-9

Used for …

MIO27

PS_JTAG

tdi

J3-90

PJTAG0_TDI → Reset PHY1 (U33)

X9-5

a bug fix!

MIO28

PS_JTAG

tdo

J3-92

PJTAG0_TDO

X9-13

MIO29

PS_JTAG

tms

J3-94

PJTAG0_TMS

X9-7

MIO30

GPIO1

gpio1[30]

J3-96

PS_1V8_GPIO7 → FrntPnl_switch7

X18-21

SW2 (ctl)

MIO31

GPIO1

gpio1[31]

J3-98

MIO31: (R135)→ isoEmergStop or (R137)→ PS…IO8

X13-9 X19-3

Jack (R137 DNP)

MIO32

SPI_1

sclk(_out)

J3-87

PS_SPI1_SCLK → isoSPI_SCLK_3V3

X12-5

MIO33

GPIO1

gpio1[33]

J3-89

PS_1V8_GPIO2 → FrontPanel_LED2

X18-15

LED2

MIO34

GPIO1

gpio1[34]

J3-91

PS_1V8_GPIO3 → FrontPanel_LED3

X18-16

LED3

MIO35

SPI_1

n_ss_out[0]

J3-93

PS_SPI1_CS → isoSPI_CS_3V3

X12-6

MIO36

SPI_1

miso

J3-95

PS_SPI1_MISO → isoSPI_MISO_3V3

X12-3

MIO37

SPI_1

mosi

J3-97

PS_SPI1_MOSI → isoSPI_MOSI_3V3

X12-2

MIO38

SPI_0

sclk(_out)

J3-102

PS_SPI0_SCLK → EXT_SPI0_SCLK

X10-4

MIO39

GPIO1

gpio1[39]

J3-104

PS_1V8_GPIO4 → FrontPanel_LED4

X18-17

LED4

MIO40

GPIO1

gpio1[40]

J3-106

PS_1V8_GPIO5 → FrntPnl_switch5

X18-19

SW3 (stp)

MIO41

SPI_0

n_ss_out[0]

J3-108

PS_SPI0_CS → EXT_SPI0_CS

X10-10

MIO42

SPI_0

miso

J3-110

PS_SPI0_MISO → EXT_SPI0_MISO

X10-9

MIO43

SPI_0

mosi

J3-112

PS_SPI0_MOSI → EXT_SPI0_MOSI

X10-3

MIO44

GPIO1

gpio1[44]

J3-101

PS_1V8_GPIO6 → FrntPnl_switch6

X18-20

SW1 (sys)

MIO45

GPIO1

gpio1[45]

J3-103

MIO45: PS_ANL_sharedA

X5*-56

MIO46

SD-Card1

data_io[0]

J3-105

MIO47

SD-Card1

data_io[1]

J3-107

MIO48

SD-Card1

data_io[2]

J3-109

MIO49

SD-Card1

data_io[3]

J3-111

MIO50

SD-Card1

cmd_io

J3-113

MIO51

SD-Card1

clk_out

J3-114

MIO52

GPIO2

gpio2[52]

J3-118

isoGPIO01

X11-9 X13-12

MIO53

GPIO2

gpio2[53]

J3-120

isoGPIO02

X11-10 X13-13

MIO54

GPIO2

gpio2[54]

J3-122

isoGPIO03

X11-11 X13-2

MIO55

GPIO2

gpio2[55]

J3-124

isoGPIO04

X11-12 X13-3

MIO56

GPIO2

gpio2[56]

J3-126

isoGPIO05

X11-13 X13-15

MIO57

GPIO2

gpio2[57]

J3-128

isoGPIO06

X11-14 X13-16

MIO58

GPIO2

gpio2[58]

J3-117

isoGPIO07

X11-1 X13-5

MIO59

GPIO2

gpio2[59]

J3-119

isoGPIO08

X11-2 X13-6

MIO60

GPIO2

gpio2[60]

J3-121

isoGPIO09

X11-3 X13-18

MIO61

GPIO2

gpio2[61]

J3-123

isoGPIO10

X11-4 X13-19

MIO62

GPIO2

gpio2[62]

J3-125

isoGPIO11

X11-5 X13-8

MIO63

GPIO2

gpio2[63]

J3-127

isoGPIO12

X11-6

MIO64

Ethernet

rgmii_tx_clk

J3-131

MIO65

Ethernet

rgmii_txd[0]

J3-133

MIO66

Ethernet

rgmii_txd[1]

J3-135

MIO67

Ethernet

rgmii_txd[2]

J3-137

MIO68

Ethernet

rgmii_txd[3]

J3-139

MIO69

Ethernet

rgmii_tx_ctl

J3-141

MIO70

Ethernet

rgmii_rx_clk

J3-132

MIO71

Ethernet

rgmii_rxd[0]

J3-134

MIO72

Ethernet

rgmii_rxd[1]

J3-136

MIO73

Ethernet

rgmii_rxd[2]

J3-138

MIO74

Ethernet

rgmii_rxd[3]

J3-140

MIO75

Ethernet

rgmii_rx_ctl

J3-142

MIO76

MDIO3

gem3_mdc

J3-143

MIO77

MDIO3

gem3_mdio(…)

J3-144

Pin capabilities#

For detailed information, see the Xilinx Technical Reference Manual of the Zynq UltraScale+ aka UG1085 (i.e., chapter Multiplexed I/O and table MIO Interfaces).